1. Technical Field of the Invention
The present invention relates to semiconductor circuits and, more particularly, to semiconductor circuits in which the bodies of at least some transistors are forward-biased.
2. Description of Prior Art
In conventional static, dynamic, and differential complementary metal oxide semiconductor (CMOS) logic and memory circuits, an n-Channel metal oxide semiconductor field effect transistor (MOSFET) (DMOS transistor) or a p-Channel MOSFET (pMOS transistor) is used with its body terminal connected to the ground or supply voltage node, respectively. Other circuit schemes have been proposed where a reverse bias is applied statically or dynamically to the body node of a MOSFET to reduce subthreshold leakage current when the MOSFET is not switching. In these schemes, the body of the pMOS transistor is connected to a voltage source larger (more positive) than the supply voltage, and the body of the nMOS transistor is connected to a voltage source smaller (more negative) than the ground potential.
The maximum achievable performance and the minimum supply voltage allowed at a desired performance level in microprocessor and communication chips which use the above-recited schemes may be limited by 1) the intrinsic transistor drive current and 2) the controllability of device parameters offered by the process technology. The predominant source of device parameter fluctuations across a die may be a variation of critical dimension (CD). In order that the MOSFET characteristics do not vary by unacceptably large amounts in response to CD-variations, the device may be carefully engineered to have sufficiently large margin for short-channel-effect (SCE), drain-induced-barrier-lowering (DIBL), and punch-through (PT) immunity. As the minimum feature size scales below, for example, 0.18 micrometers, the available design space for construction of a MOSFET which provides sufficient drive current at low supply voltages while maintaining adequate SCE, DIBL, and PT immunity becomes severely restricted. These design challenges for ultra-small bulk MOSFETs can pose a major barrier to achieving the performance and power goals in future generations of microprocessor, communication, and memory chips. In addition, these design difficulties can cause the development cost of future process technologies to escalate by large amounts.
Accordingly, there is a need for transistors that provide relatively high performance at relatively low power.
One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage, and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors.
Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage, and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage, and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage, and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.